Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - pci VHDL

Search list

[Other resource] PCI

Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.
Platform: | Size: 899078 | Author: lee | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[Other] PCIcropbyvhdl

Description:
Platform: | Size: 420864 | Author: 秦淅 | Hits:

[VHDL-FPGA-Verilog] pci_express_crc

Description: PCI express CRC rtl core for Fpga/asic Designer
Platform: | Size: 202752 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] pci9030

Description: pci9030接口，可以实现与pci9030芯片的接口，-pci9030 interface can be achieved with pci9030 chip interface,
Platform: | Size: 1024 | Author: jz | Hits:

[Embeded-SCM Develop] 9054

Description: PCI总线的高速数据采集卡设计资料（基于PCI9054 ）-PCI-bus high-speed data acquisition card design information (based on PCI9054)
Platform: | Size: 2058240 | Author: 斌 | Hits:

[Software Engineering] PCIE_Spec_1.1

Description: PCI express 开发文档，有详细的对协议的介绍。-PCI express development of documents, has a detailed introduction of the agreement.
Platform: | Size: 4958208 | Author: 屈均伟 | Hits:

[File Format] asic_design

Description: 华为,大规模逻辑设计指导书,规格详细，包括：VHDL编写规范，Verilog编写规范，asic设计方法，同步电路设计规则，vhdl电路设计，代码可重用设计，-Huawei, a large-scale logic design guide books, detailed specifications, including: VHDL specification preparation, Verilog specification preparation, asic design, synchronous circuit design rules, vhdl circuit design, reusable code design,
Platform: | Size: 2041856 | Author: feng jee | Hits:

[VHDL-FPGA-Verilog] pci_t

Description: verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
Platform: | Size: 10240 | Author: 齐培红 | Hits:

[VHDL-FPGA-Verilog] DMA_Freeware

Description: 基于xilinx vierex5得pci express dma设计实现。-Based on a xilinx vierex5 realize pci express dma design.
Platform: | Size: 12781568 | Author: liu | Hits:

[VHDL-FPGA-Verilog] datapath_fifo

Description: datapath_fifo used in DMA contect PCI in the DAB system the format of this file is VHDL
Platform: | Size: 1024 | Author: hjy | Hits:

[VHDL-FPGA-Verilog] pciug159

Description: XILINX ISE生成PCI-CORE时产生的用户文档,帮助编写PCI通信用户逻辑,非常有用-XILINX ISE generation PCI-CORE generated user documentation to help users prepare PCI communication logic, a very useful
Platform: | Size: 1374208 | Author: 田杰 | Hits:

[VHDL-FPGA-Verilog] PCI_VHDL

Description: vhdl实现pci，找了很久才下到。应该比较适合设计-vhdl implementation pci, looking for a long time before the next to. Should be more suitable for design
Platform: | Size: 106496 | Author: fantasy | Hits:

[SCM] PCI_express_layers

Description: PCI express layers doccuments
Platform: | Size: 397312 | Author: arsal | Hits:

[Embeded-SCM Develop] This_is_pci-wishbone_nuclear_and_16450_serial_port

Description: 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
Platform: | Size: 8428544 | Author: iceskull | Hits:

[VHDL-FPGA-Verilog] PCI9052

Description: 用verilog语言编译的pci协议实现，而且有具体的电路图-Compiled with the verilog language pci protocol implementation, but also the specific circuit
Platform: | Size: 1941504 | Author: 李超 | Hits:

[Software Engineering] 105230299PCI-IPcoreor1k[1]

Description: nios connection with bus avalon
Platform: | Size: 1064960 | Author: sahbi | Hits:

[VHDL-FPGA-Verilog] FPGAPCI

Description: 本资料是永远FPGA的PCI接口代码，vhdl写的，已经通过仿真认真。-this is a good ziliao about pci。
Platform: | Size: 845824 | Author: 秦天 | Hits:

[VHDL-FPGA-Verilog] testbench

Description: altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
Platform: | Size: 1759232 | Author: greenpine | Hits:

[VHDL-FPGA-Verilog] sdram_pci

Description: 基于SDRAM的PCI采集程序，PCI9054控制器+SDRAM控制器Verilog源代码，，已经SignalTap调试通过。-SDRAM PCI-based acquisition program, PCI9054 Controller+ SDRAM controller Verilog source code, has SignalTap through debugging.
Platform: | Size: 3166208 | Author: wangbo | Hits:
« 1 2 3 45 6 7 »

CodeBus www.codebus.net